| 摘要 |
PROBLEM TO BE SOLVED: To suppress increase of interconnection resistance due to vaporization without increasing the memory cell area by coating a high melting point metal with tungsten silicide and then exposing and oxidizing a polysilicon. SOLUTION: A gate oxide 2, a polysilicon 3 serving as the lower part of a gate electrode, a first tungsten nitride 16, and a tungsten 5a serving as the upper part of the gate electrode are deposited on a P type semiconductor substrate 1. A first silicon nitride 6 is then deposited on the tungsten 5 and etched to form the upper part of a gate electrode. Subsequently, a second tungsten nitride 14 and a first tungsten silicide 15 are deposited and etched back to form a sidewall. Thereafter the polysilicon 3 is exposed by etching to form the lower part of the gate electrode. Finally, the sidewall and the lower end part of polysilicon are rounded 7, 8 and a source-drain region 9 is formed by ion implantation.
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