| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten the test period and to improve the productivity by eliminating the need for a holding test even when a low-speed mode is set, by setting the signal hold period of a dynamic circuit to the time of one original oscillation clock width even when a system clock is set slow. SOLUTION: System clocks CKO 30 to CK2 32 are connected to the control signal for a dynamic holding operation and CK3 33 is connected to the control signal for a static operation. A data signal 24 is set to '1'. Then, CK1: 31 is inputted to a static latch 35 in timing of '1' and a system clock switching signal 27 becomes '1' to select the operation of a slow system clock. Consequently, CK0 to CK2 output '1' in order with the cycle width of one original oscillation clock in order and operate, but when CK3 reaches timing of '1', CK3 33 holds the timing of '1' until a 4th frequency-divided signal 12 rises. Thus, the dynamic circuit is supplied with the short-cycle pulses to operate and the need for a holding test using slow cycle pulses is eliminated.</p> |
