发明名称 |
INTERPOLATION LOOK-UP TABLE CIRCUIT AND DETERMINING METHOD FOR INTERPOLATION VALUE |
摘要 |
PROBLEM TO BE SOLVED: To make LUT output highly precisely by outputting an interpolation LUT circuit output signal by combining a multiplier output signal with bit group parts of a selected LUT entry. SOLUTION: An input signal has 1st bit groups including the Q bits of a 1st part and the N-Q bits of a 2nd part. A selector circuit 12 receives QMSB of an N-bit input signal. The selector circuit 12 selects the LUT entry which is the most closest to the 1st part of the input signal. A combining circuit 14 combines the inputted signal and a multiplier 15 outputs its multiplier output signal onto a line 15b. An adder 16 receives the multiplier output signal appearing on a line 15b and the value part of the selected LUT entry appearing on a line 6a. The adder 16 adds the inputted signal and outputs its adder output signal onto a line 16a and this output signal is inputted to a rounding circuit 17 which is coupled with the adder 16 so that it can operate.
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申请公布号 |
JPH1185964(A) |
申请公布日期 |
1999.03.30 |
申请号 |
JP19980185454 |
申请日期 |
1998.06.30 |
申请人 |
TRUEVISION INC |
发明人 |
DUVANENKO VICTOR J;SHUMARD ERIC |
分类号 |
H04N5/202;G06F1/035;G06F17/17;G06T1/20;(IPC1-7):G06T1/00 |
主分类号 |
H04N5/202 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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