发明名称 |
OPERATION METHOD AND ARITHMETIC UNIT |
摘要 |
PROBLEM TO BE SOLVED: To reduce the circuit scale of a digit adjusting means and to efficiently realize a double precision multiplication. SOLUTION: In a binary fixed point system for setting up a most significant bit(MSB) as a code bit S and a point between the MSB and a bit just under the MSB as a binary point position, respective products between the higher word HX/lower word XL of a double precision multiplicand and the higher word YH/lower word YL of a double precision multiplier are found out by using a single precision multiplier, and in the case of executing the adjusting addition of respective found products to obtain a double precision multiplied result, respective products between the higher word XH/lower word XL of a double precision multiplicand and the higher word YH/lower word YL of a double precision multiplier are set up so as to have at least two digits higher than the binary point position, so that the double precision multiplied result can be found out by bit width more than double precision bit width at least one bit. |
申请公布号 |
JPH1185471(A) |
申请公布日期 |
1999.03.30 |
申请号 |
JP19980187061 |
申请日期 |
1998.07.02 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
TAGAMI KAZUFUMI;KABUO HIDEYUKI;YAMANAKA RIYUUTAROU |
分类号 |
G06F7/52;G06F7/527;G06F7/533 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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