| 摘要 |
An apparatus to improve the speed of handling of denormal numbers in a computer system, the apparatus comprising a mode bit and a selector, the mode bit set when denormals are to be replaced by zero, the selector having a first input and an output, the first input comprising a floating point number, the selector selecting zero to become the output when the floating point number is denormal and the mode bit is set, the selector selecting the floating point number to become the output otherwise. |
