| 摘要 |
A back bias voltage level detector includes a reference voltage generator outputting a reference voltage having a constant voltage, a PMOS pull-up transistor coupled to the reference voltage generator and an external voltage and outputting a gate-source voltage of the PMOS pull-up transistor, an NMOS pull-down transistor coupled to the PMOS pull-up transistor and a back bias voltage and outputting a gate-source voltage of the NMOS pull-down transistor, a couple of inverters connected in series between the PMOS pull-up transistor and the NMOS pull-down transistor and outputting an oscillation enable signal, and a couple of resistors connected in series between the back bias voltage and a ground voltage and connected to the NMOS pull-down transistor.
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