发明名称 |
SIGNAL PROCESSING DELAY APPARATUS |
摘要 |
A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit. |
申请公布号 |
KR0166140(B1) |
申请公布日期 |
1999.03.20 |
申请号 |
KR19950009626 |
申请日期 |
1995.04.24 |
申请人 |
HITACHI LTD. |
发明人 |
WATANABE, KUNIO;HASE, KENICHI;HORITA, RYUTARO;ISHIDA, YOSHITERU;NARA, TAKASHI;KIMURA, HIROSHI |
分类号 |
G11B5/09;G11B20/10;G11B20/14;H03H11/26;H03H11/54;H03K5/13;H03K5/135;H03L7/081;H03L7/089;H03L7/099;H04L7/00;H04L7/02;(IPC1-7):H03H9/00 |
主分类号 |
G11B5/09 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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