| 摘要 |
A system and method for converting data between a multi-bit time division multiplexed bus and a faster single-bit TDM bus, wherein each TDM bus communicates data by means of frames, each frame comprising a fixed number of slots and each slot comprising a fixed number of bits. A fast bus to slow bus conversion circuit comprises a parallel shift register (500), a synchronization latch (502), buffer latch (504), a fast bus slot/bit counter (506), on edge detector (510) coupled to a phase resolution circuit (512) and a fast-sync generator (508). The circuit uses purely digital technique to perform synchronization.
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