PERTURBATION TOLERANT DIGITAL PHASE-LOCKED LOOP EMPLOYING PHASE-FREQUENCY DETECTOR

摘要

A digital phase-locked loop less susceptible to perturbations has a phase-frequency detector receiving a reference clock and the output of a voltage controlled oscillator, a loop filter receiving the output of the phase-frequency detector, a voltage-controlled oscillator receiving the output of the loop filter for providing the phase-locked loop output, a divide-by-N counter also receiving the output of the voltage-controlled oscillator for providing an input to the phase-frequency detector, and a monitoring counter for determining whether there are N plus or minus "a" voltage-controlled oscillator clock pulses between each successive reference clock pulse, where "a" is slightly larger than the number of clock pulses which when added or subtracted from the number of clock pulses corresponding to the nominal frequency of the phase-locked loop would cause the maximum desired frequency deviation of the phase-locked loop output from the nominal frequency, the monitoring counter reloading the divide-by-N counter and resetting the phase-frequency detector when there are fewer than N-a clock pulses between consecutive reference clock pulses and resetting the phase-frequency detector when there are more than N+a clock pulses between consecutive reference clock pulses.