| 摘要 |
PROBLEM TO BE SOLVED: To reduce glitches generated and propagated in a circuit and to reduce power to be consumed by the glitches by deforming the constitution of the circuit in order to reduce power consumption in register transfer level(RTL) design. SOLUTION: In the case of reducing glitches in a logic circuit, a multiplexer, etc., a glitch in a control signal, is reduced by adding a gate to the logic circuit, reconstituting the multiplexer or clocking the control signal. A glitch in a data signal is reduced by selectively delaying a control signal, reconstituting the multiplexer or clocking the control signal. In addition, a circuit for suppressing unnecessary clock transition is added to reduce power to be consumed in a register. Then an optimum change for the reduction of power consumption out of the described technique is automatically selected and applied, and while reevaluating the application result, the application is repeated in all levels of the circuit. |
