Hierarchical interconnect for programmable logic devices

摘要

A hierarchical interconnect structure between logic elements, logic array blocks and global interconnects in a programmable logic device is disclosed. The present invention provides a first group of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic element in one block in an area efficient manner.