| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device employing an automatic layout and routing using a floor plan of an internal IO method, and also, enhance chip performance, improve quality, reduce the area, and reduce man-hours. SOLUTION: For example, this device is assumed to be a synchronous cache SRAM of eight-macro cell constitution. In the semiconductor chip, the length (Y) axis is divided into the region of 11 rows over the direction of side (X), and RAM macro cell region A, IO cell region B, and the standard cell region C are allocated. In the chip layout design, standard cell region C is arranged between RAM macro cell region A and IO cell region B. Also, heights of both a FUSE macro cell 10 and a PLL macro cell 11 match the IO cell, and the FUSE macro cell 10 and the PLL macro cell 11 are arranged in an empty region in this IO cell region B. In addition, an IO cell group 9 is arranged in the lower layer of an internal bump group 20. |
