发明名称 Forming self-aligned vias in a semiconductor device
摘要 A process for forming a via in a semiconductor device uses a self-aligned metal column to connect metal layers separated by a dielectric. A via is formed in a semiconductor device by: (a) forming three overlying conductive layers on a semiconductor substrate, the second layer being of different material from the first and second layers; (b) simultaneously etching the layers to form a patterned section and to expose part of the substrate; (c) filling the etched gaps with a first dielectric layer which is then planarized to expose the top surface of the patterned section; (d) etching a section of the third conductive layer, using the second conductive layer as an etch-stop, to form a column; and (e) filling the etched gaps with a second dielectric layer which is then planarized to expose the top surface of the column.
申请公布号 DE19834917(A1) 申请公布日期 1999.03.11
申请号 DE19981034917 申请日期 1998.08.03
申请人 NATIONAL SEMICONDUCTOR CORP., SANTA CLARA, CALIF., US 发明人 KITCH, VASSILI, SAN RAMON, CALIF., US
分类号 H01L21/768;(IPC1-7):H01L21/768 主分类号 H01L21/768
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