| 摘要 |
<p>A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction setting register (11) to which the CPU (1) sets a wait instruction and a wait cancel instruction; and a wait controller (12) for outputting a wait signal to the wait terminal (9) of the CPU (1) in accordance with the setting of the register (11), wherein the inventive data processor allows a wait state to be set and canceled as programmed independently of address space constraints. <IMAGE></p> |
