| 摘要 |
A synchronous delay circuit of multiplex configuration is disclosed that has a delay time that corresponds to the pulse separation immediately preceding input of the pulse signal. For the purpose of reducing dependence of the delay time differential between the delay signal and the external clock signal upon the external clock signal cycle, the multiplex synchronous delay circuit of this invention is provided with a plurality of synchronous delay circuits; a delay time differential that is smaller that the delay time of each gate section of the delay circuit bank that make up each of these synchronous delay circuit is arranged at the input/output portion of the signal path of the synchronous delay circuits, and the outputs of these synchronous delay circuits are multiplexed by their logic output. <IMAGE> |
