| 摘要 |
<p>PROBLEM TO BE SOLVED: To change the phase of variable length data without abandoning excessive data even when the variable length data are generated by performing write without finishing write to a 1st 2-port RAM even after the writing operation of a cell is finished and the writing operation of the next cell is started. SOLUTION: An internal write signal A13 and an internal write signal B14 are managed by a write control part 3 and it is managed whether these signals are to be written into a 2-port RAM 1 or 2. The internal write signals A13 and B14 are alternately sent for the unit of a cell in a write pulse signal 11. At such a time, even while the internal write signal B14 is sent out by the write pulse signal 11, the internal write signal A13 is continuously sent out by the next write pulse signal. Thus, when the variable length data to be used for controlling the device are inputted, the next write pulse signal 11 is delayed so that the input data are written in the 2-port RAM 1 as they are.</p> |
