Synchronous semiconductor memory device allowing fast operation in either of prefetch operation and full page mode operation

摘要

SDRAM 1000 outputs data, in a 2-bit prefetch operation, by simultaneously selecting two columns in memory cell array banks A0 and A1 in accordance with column select signals YE0-YEk and YO0-YOk issued from Y-address operation circuit 68. In a full page mode, data are output from all columns crossing rows alternately selected in memory cell array banks A0 and A1 in accordance with an internal address signal issued from a Y-address counter circuit 82.