| 摘要 |
A dual delay-locked loop is employed to reduce timing skew between two signals, such as localized clock signals, which are both derived from a common input signal. Individually controllable variable delay circuits are used in the signal paths between the common input signal and each of the two signals to nominally create additional delay between the common input signal and each of the two signals. The two signals are compared, the timing skew therebetween is indicated, and the variable delay circuits are each adjusted to reduce the skew between the two signals. The common input signal is not used as a reference signal for the comparison. Rather, the two variably-delayed signals themselves are compared, and both variable delays are adjusted to reduce the skew. If the first signal (of the two signals) is indicated as lagging the second signal, the variable delay circuit in the path of the first signal is typically, although not necessarily, decreased, and the variable delay circuit in the path of the second signal is typically increased. By adjusting both delays, a faster settling time is achievable compared to using only a single loop circuit. A wide variety of signal frequencies may be accommodated by using variable delay circuits which provide for a selectable maximum delay. The variable delay circuits may be configured using a plurality of serially-connected gates, which may include a variable RC load circuit at each output.
|
