发明名称 BINARY/DECIMAL CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a binary/decimal conversion circuit improving conversion speed with a small circuit scale. SOLUTION: The circuit is provided with a reading '1' detection circuit 13 detecting the number of the bits of '0' until the bit of '1' appears at first in a period from the highest bit of binary data to n-bits, a shift circuit 14 shifting binary data to the highest side by the detection value, decimal multiple generation circuits 15 generating the multiples of decimal data and a decimal data selector 16 selecting one of the decimal multiple generation circuits 15. One of the multiple to (n+1)-th power multiple of 2 in decimal data, which are generated by the decimal multiple generation circuits 15 with the detection value of the reading '1' detection circuit 13, is selected. The lowest one bit is substituted for the highest one bit of data shifted to the highest side with the shift circuit 14 by the detected value. Thus, parts where n-pieces of the bits of '0' of binary data being conversion objects continue arc collectively converted into decimal data.
申请公布号 JPH1165820(A) 申请公布日期 1999.03.09
申请号 JP19970229887 申请日期 1997.08.26
申请人 KOFU NIPPON DENKI KK 发明人 SHIMIZU HIROSHI
分类号 G06F7/00;G06F7/38;G06F7/483;G06F7/493;G06F7/74;H03M7/06 主分类号 G06F7/00
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