| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a vertical timing signal generating circuit which operates stably, regardless of the phase relation between a vertical synchronization signal and a vertical timing signal which is generated by a counter and which is capable of obtaining the vertical timing signal having a desired phase. SOLUTION: A delay circuit 100 inputs a vertical synchronization signal Pc123 and outputs a signal, whose phase is delayed with respect to the inputted vertical synchronization signal Pc123 by a prescribed phase as a reset signal Pc125 and after a vertical counter 103 inputs a horizontal synchronization signal Pb121 and the reset signal Pe125 outputted from the delay circuit 100 for resetting a count by using the reset signal Pe125 and counts the horizontal synchronization signal Pb125 only up to a prescribed number, and subsequently the counter 103 outputs a vertical timing signal Pd127.</p> |
