| 摘要 |
PROBLEM TO BE SOLVED: To provide a counter that enables a high-speed operation and can reduce power consumption at the time of a slow-speed operation. SOLUTION: A programmable counter 14 is equipped with a high-speed counter part 14a, a low-speed counter part 14b and a switch circuit SW, and frequency-divides an input signal fvco by a set rate N of frequency division. The high-speed counter part 14a is constituted by using an MOS transistor of a long-channel width. The low-speed counter part 14b is constituted by using an MOS transistor of a short-channel width. The switch circuit SW selects either of the high-speed counter part 14a or the low-speed counter part 14b on the basis of a selection signalϕ, corresponding to the input signal fvco frequency.
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