| 摘要 |
An improved DRAM is disclosed, in which a number of sense amplifiers to be activated simultaneously can be selected by using a bonding option method. An output signal / phi A supplied from a bonding option circuit 11 is applied to column interlock releasing circuit 7. When an operation mode in which the number of the sense amplifiers to be activated simultaneously is large is selected, a column interlock releasing signal / phi is delayed, and enabling of a column decoder 3 is delayed. In the operation mode, in which the number of the sense amplifiers to be activated simultaneously is large, the enabling of the column decoder 3 is delayed, and a conducting timing of an IO gate circuit 16 is delayed. A sense amplifier 15 can sufficiently amplify a potential difference between bit lines, so that an error in the data reading operation is prevented. |
