A RECONFIGURABLE ARITHMETIC DATAPATH

摘要

A method and apparatus that combine the same basic hardware elements in several ways to perform a plurality of arithmetic operations over different numbers of operands of different lengths. The allowed options include the multiplication (120) and summing of several operands in a single operation. The reuse of ha rdware elements is obtained by the use of a multiplication hardware (120) structure together with multiplexer (122) logic (or similar selection logic) at appropriate points in the hardware structure, which allows a minimum of extra hardware and a small number of extra gate delays along any critical path, thereby ensuring that the flexibility to use different operand lengths and numbers of operands incurs only a small penalty in processing speed and/or chip area in a VLSI circuit implementation.