The device has a memory cell field with first memory cells (S1)using vertical MOS transistors and second memory cells (S2) without MOS transistors. The memory cells are formed in the walls of parallel grooves (4) across the cell field, with a gate dielectric in the vicinity of each of the first memory cells covered by a gate electrode. The part of the groove wall incorporating each second memory cell is covered with an insulation material e.g. TEOS the groove filled between adjacent memory cells of first and second type with the gate dielectric and a second insulation material e.g. TEOS or BPSG. The gate electrodes are coupled to word lines (9) extending across the grooves.
