High reliability I/O stacked fets

摘要

The effects on device reliability of across chip length variation (ACLV), gate ion channeling and dislocation are reduced or eliminated in input/output (I/O) stacked field effect transistors (FETs). A pair of stacked PFETs and a pair of stacked NFETs are connected to an I/O pad. The PFET and the NFET adjacent to the I/O pad are designed with a channel length greater than the PFET and NFET, respectively, further removed from the I/O pad. This has the effect of making the PFET and NFET adjacent to the I/O pad insensitive to leakage-induced effects. Alternatively, a Schottky or P/N junction diode may be connected between the node between the gate of the PFET adjacent to the I/O pad and the two PFETs, and another Schottky or P/N junction diode may be connected between the node between the two NFETs and the gate of the NFET adjacent to the I/O pad. The Schottky diodes act to clamp the nodes between the pair of PFETs and the pair of NFETs near the respective gate voltages. A similar clamping action can be accomplished using an NFET in place of the Schottky or P/N junction diode for the pair of PFETs and a PFET in place of the Schottky or P/N junction diode for the pair of NFETs.