| 摘要 |
PROBLEM TO BE SOLVED: To prevent excessive pulses from being inputted to the PLL circuit by setting the pulse width of an input clock outputted to the PLL circuit to a period of a half to one cycle based upon a rise of an input pulse. SOLUTION: The period wherein a NOR circuit 215 outputs an 'H' level is determined by the time constant determined by the resistance value R of a resistance 213 and the capacity C of a capacitor 212. Namely, an output (f) can be held at the 'H' level for the period determined by the capacitor 212 and resistance 213 independent of the input clock inputted to a timer circuit 2. Therefore, even if an input clock having excessive pulses is inputted to the timer circuit 2, the excessive pulses can be masked, thereby providing the PLL circuit with the input clock selecting circuit which is not affected by the excessive pulses. |
