发明名称 FAILURE SIMULATION METHOD, DEVICE, AND MEMORY MEDIUM STORING FAILURE SIMULATION PROGRAM
摘要 PROBLEM TO BE SOLVED: To secure a sufficient diagnostic factor by writing a failure value in a memory circuit when a failure propagated to the memory circuit exists at a front circuit portion, and propagating it to a rear circuit portion at the later observation time. SOLUTION: A circuit separation section 1 separates an integrated circuit into a rear circuit portion on the output pin side of a memory circuit and a front circuit portion on the input pin side. A parallel pattern failure simulation section 6 injects a failure to the integrated circuit and propagates it and detects the failure based on the difference between the result at an observation point and the normal value simulation result of a parallel pattern normal value simulation section 5. When the failure propagated to the input pin of the memory circuit exists at the front circuit portion in the circuit state at this observation time stored in a circuit state storage section 7, a failure transit section 8 writes the failure value at this observation time in the memory circuit. The failure value is read out at the later observation time and is propagated to the rear circuit portion from the output pin. The failure at the front circuit portion can be handled as a detection object, and a sufficient diagnostic factor can be secured.
申请公布号 JPH1138098(A) 申请公布日期 1999.02.12
申请号 JP19970198608 申请日期 1997.07.24
申请人 FUJITSU LTD 发明人 MARUYAMA DAISUKE
分类号 G01R31/28;G06F11/22;G06F11/26;G06F17/50 主分类号 G01R31/28
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