Kupferbasierte Metallisierung für hybride integrierte Schaltungen

摘要

The circuit includes thin film elements and electrical interconnections on a major surface of an insulating substrate. The interconnections comprise: a first metal layer comprising Ti formed on the substrate; a second metal layer comprising an alloy of Ti and Pd formed on the first metal layer, and comprising 0.3-14 wt.% Pd; third and fourth metal layers comprising Cu and Ni respectively, formed sequentially on the second layer; and a fifth metal layer comprising Au formed on at least portions of the fourth metal layer. Pref. layer thicknesses all as follows: first metal layer 100-300 nm; second metal layer 50-300 nm; third metal layer 2500-4000 nm; fourth metal layer 800-2000 nm; and fifth metal layer 700-2500 nm. The fifth metal layer may be formed on the entire surface of the fourth layer, or only on portions of the fourth layer which comprise bonding pads for the circuit.