| 摘要 |
<p>The power consumption of a digital matched filter for finding the value of the correlation between 6-bit digital signals (I0) synchronized with a clock and an inverse spectrum spread code sequence composed of eight inverse spectrum spread codes (C7, C6, C5, C4, C3, C2, C1, and C0) is reduced. First to eighth flip-flops (211-218) constituting a storing section (210) are successively selected one by one at a clock by means of a write selecting circuit (220), and the digital signals (I0) are stored in the selected flip-flops. The eight inverse spectrum spread codes are respectively stored in first to eight flip-flops (231-238) for code storage and shifted synchronously with the clock. The output signals of the first to eighth flip-flop are respectively multiplied by the output signals of the first to eighth flip-flops (231-238) for code storage by means of first to eight multiplying circuits (241-248).</p> |
