发明名称 |
Video decoder |
摘要 |
<p>An image processing apparatus which performs motion compensation prediction image decompression by a small circuit scale. The apparatus comprises: an image memory which is equivalent to a processing region and executes the motion compensation; and an adder. The adder executes interpolation calculation in the event that a reference image is constructed from a motion vector of 1/2 accuracy, and its result therefrom is stored in said image memory. Addition process of the reference image and difference data is processed by the same adder in a time sharing manner. <IMAGE></p> |
申请公布号 |
EP0896478(A2) |
申请公布日期 |
1999.02.10 |
申请号 |
EP19980117178 |
申请日期 |
1994.06.27 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
DEMURA, TATSUHIKO;KITAGAKI, KAZUKUNI;OTOMO, GOICHI |
分类号 |
H04N7/32;H04N7/26;H04N7/36;H04N7/50;(IPC1-7):H04N7/50 |
主分类号 |
H04N7/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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