发明名称 |
DRAM sensing scheme for eliminating bit-line coupling noise |
摘要 |
A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by connecting only one bit line within one sub-array to be connected to a sense amplifier, while the complementary bit line used for the reference voltage of the sense amplifier is selected from an adjacent sub-array, is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.
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申请公布号 |
US5870343(A) |
申请公布日期 |
1999.02.09 |
申请号 |
US19980055443 |
申请日期 |
1998.04.06 |
申请人 |
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
CHI, MIN-HWA;LIN, MING-ZEN |
分类号 |
G11C7/06;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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