NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF

摘要

PROBLEM TO BE SOLVED: To hold the conventional floating gate potential with a low control gate potential by comprising aux. control gates (first gate electrodes) in addition to floating gates (second gate electrodes) and control gates (third gate electrodes). SOLUTION: At erasing, a control gate electrode voltage VCG1 and aux. control gate electrode voltage VCG2 are set to 0 V and substrate voltage Vsub to an erase potential VPPe to enable the erase. At writing, the control gate electrode voltage VCG1 and aux. control gate electrode voltage VCG2 of a selected memory cell are set to a write potential VPPW, the substrate voltage Vsub to 0 V, and the control gate of a not selected memory cell is set to 0 V or bit line medium potential VMWL to enable the write. This allows the applied voltage at erasing to lower and hence the peripheral circuits and chip area to be reduced.