Automatisches Entwurfsverfahren für digitale elektronische Schaltkreise

摘要

A design automation method for digital electronic circuits, including the steps of synthesizing a circuit including at least one logic tree, and then automatically partitioning the logic tree. The automatic partitioning process involves first identifying a set of driving bits for each of a set of points within the tree, ie the tree inputs that affect each of those points. Then, for each of those points, the partitioning process identifies a set of splittable input bits that can be isolated by insertion of a fence register at that point, and identifies which of those points are possible fence points, having more than one splittable input bit. Finally, the partitioning process selects a sub-set of the possible fence points, sufficient to reduce the number of inputs to the logic tree to a value less than a predetermined limit, and inserts fence registers at those points. In this way, the number of inputs to the logic tree can be made small enough (e.g. 17 or less) to allow exhaustive testing of the circuit.