发明名称 Integriertes Schaltungsbauelement hoher Dichte
摘要 A 3-dimensional circuit assembly includes a lower substrate (6a), a first integrated circuit (IC) layer (10b) that is adhered to and electrically insulated from the substrate (6a), electrical contacts (18) for the IC layer (10b), and separate electrical contacts for the substrate (6a) that extend through and are insulated from the IC layer (10b). The IC layer (10b) is surmounted by an insulating layer (8b) through which the electrical contacts (18) also extend, and across which interconnections (20) between different contacts may be made. The IC layer (10b) and substrate (6b) are held together by an adhesion layer (4), with the adhesion (4), IC (10b) and insulating (8b) layers all being thin enough to assume the coefficient of thermal expansion for the underlying substrate (6a), which is much thicker. The substrate (6a) may itself have a second IC layer (10a) to which contacts are made, or it may be implemented as the photodetector of a focal plane array. Two standard wafers (2a, 2b) are used to form the package, with the substrate (6b) for the upper wafer (2b) removed either before or after bonding to the lower wafer (2a). Additional IC layers (10c) may be added by adding additional wafers (2c) in a similar fashion. <IMAGE> <IMAGE>
申请公布号 DE69322630(D1) 申请公布日期 1999.01.28
申请号 DE1993622630 申请日期 1993.07.22
申请人 RAYTHEON COMPANY, EL SEGUNDO, CALIF., US 发明人 GATES, JAMES L., PORTLAND,OREGON 97224, US
分类号 H01L21/58;H01L21/98;H01L23/48;H01L25/065;(IPC1-7):H01L23/538;H01L21/768;H01L21/48 主分类号 H01L21/58
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