| 摘要 |
A process and structure are described wherein logic and memory share the same chip. Contacts to the memory circuits are made using the SAC process, thus ensuring maximum density, while the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first forming polysilicon gate pedestals, those located in the memory areas also having hard masks of silicon nitride. Next, spacers are grown on the vertical sides of the pedestals. Source/drain regions are now formed using the LDD process following which the pedestals, on the memory side only, are given a protective coating of oxide (RPO). This allows the SALICIDE process to be selectively applied to only the logic side. Then, while the logic side is protected, the SAC process is applied to the memory side. This process is self-aligning. The spacers define the contact holes and the hard masks allow oversize openings to be etched without the danger of shorting through to the pedestals. |
