发明名称 SUBSTRATE FOR SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
摘要 PROBLEM TO BE SOLVED: To make peeling to hardly occur at the bottom of a via hole even when the diameter of the via hole is reduced by forming recessed sections having a specific depth on the surface of the land for via hole of a first wiring layer connected to a second wiring layer. SOLUTION: A land 11 for via hole is formed on a first insulating layer 10 and many recessed sections 12 are formed on the surface of the land 11. When the recessed sections 12 are formed, the depths of the sections 12 formed on the land 11 are measured by using a laser film thickness meter. After measurement, an insulating layer 14 having a hole 13 is obtained by applying an insulating resin and exposing and developing the resin. Then a via hole is formed by performing plating on the insulating layer 14. In addition, a second wiring layer 15 is similarly formed by etching and, at the same time, a via hole 16 is formed. Thereafter, a second insulating layer is formed through a similar process and a third wiring layer is formed. In addition, the third wiring layer is protected by forming a solder resist.
申请公布号 JPH1117332(A) 申请公布日期 1999.01.22
申请号 JP19970162821 申请日期 1997.06.19
申请人 TOPPAN PRINTING CO LTD 发明人 OFUSA TOSHIO;ISHII TOSHIAKI;MOCHIZUKI TETSUO;NAKAMURA TAKASHI
分类号 H05K3/24;H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/24
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