Normalisation circuit arrangement

摘要

The circuit includes an AND gate (8) outputting the AND result of a reference signal, produced by a mantissa input, and an exponent input. An OR gate (9) calculates an OR combination of all bits output from the AND gate. A leading-bit detector (5) records the position of a leading one of the mantissa input and produces a signal if only one bit is set at the position. A priority encoder (2) subtracts one from the bit position value. A one-bit shifter (21) shifts all bits of the signal from the leading-bit detector, with the exception of a highest-order bit, for one bit position toward the right. A selection circuit (7a) provides the output of the one-bit shifter as all bits of a control signal, with the exception of its highest-order bit, if the output of the OR gate is one, and a binary value of null if the output of the OR gate is zero.