Non-volatile memory array of EEPROM cells

摘要

A non-volatile memory array, with several EEPROM cells, floating gates (38), control gates (40) and source/drain regions, has: (a) word lines (40) connected to the control gates (40) in the column direction and spaced apart in the row direction; (b) bit lines (33a, b) connected to the source/drain regions and extending at right angles to the word lines (40); (c) programming lines (41) extending parallel to the bit lines (33a, b), one programming line being provided for each bit line; and (d) programming gates (35) connected to the programming lines (44) and used for programming the floating gates (38) adjacent each programming gate (35). Also claimed are: (i) a similar array in which one programming line is provided for and is located between two adjacent paired cells, one programming gate being provided for each cell pair and being located between the floating gates; and (ii) the production of a non-volatile semiconductor memory device.