| 摘要 |
The arrangement includes a channel estimator (KS), a data estimator (D), and a channel decoder (FD), whereby at least parts of the data estimator are implemented through modules (E4 to E14), in at least one digital signal processing device (DSP), and whereby at least parts of the modules are implemented in parallel. The modules may be distributed on several processing devices (DSP1, DSP2, DSP3, DSP4), and the signal processing device is preferably formed in such way, that the connection of the modules results according to a Petri network.
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| 申请人 |
SIEMENS AG, 80333 MUENCHEN, DE |
发明人 |
SCHLEE, JOHANNES, DIPL.-ING., 67657 KAISERSLAUTERN, DE;WEBER, TOBIAS, DIPL.-ING., 67731 OTTERBACH, DE;BAIER, PAUL WALTER, PROF. DR.-ING.HABIL., 67661 KAISERSLAUTERN, DE;MAYER, JUERGEN, DIPL.-ING., 67105 SCHIFFERSTADT, DE;EUSCHER, CHRISTOPH, DIPL.-ING., 46414 RHEDE, DE;BAHRENBURG, STEFAN, DIPL.-ING., 81477 MUENCHEN, DE |
