| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten the setup/holding time of an input signal by setting the same timing for latching an external input signal by generating the latch signal so as to generate the input signal of an LSI at the same time at all surrounding parts. SOLUTION: The output terminal of a gate 1 generating latch signals is connected to the respective one edge of loop-shaped wirings 2 and 3 surrounding the periphery of a semiconductor chip, so that the latch signals advance in the reverse directions to each other. Each other end is opened, and a plurality of integrating circuits 5 are arranged at the arbitrary positions of the chip periphery part. When an external input signal is synchronized with a latch inner signal with a latch 7 by the signal of an inverter 6, the signals of the wirings 2 and 3 are integrated with the integrating circuit 5 when a signal A is outputted from the gate 1 at a position (x). When the sum reaches the specified threshold value of the inverter 6, the external signal is latched. Therefore, all the latches 7 do not depend on the position of (x), and the external input is latched at the same time after the rising of the output of the gate 1.</p> |
