SEMICONDUCTOR INTEGRATED CIRCUIT, SYSTEM FOR REDUCING SKEW BETWEEN CLOCK SIGNAL AND DATA SIGNAL AND ITS METHOD

摘要

PROBLEM TO BE SOLVED: To reduce a skew between a clock signal and a data signal by providing a phase difference reducing circuit for reducing a first phase difference between the clock signal and the data signal and a circuit for receiving the data signal where the first phase difference is reduced. SOLUTION: The delay quantity of the phase difference reducing circuit 22 is decided in an initializing period. The delay quantity is decided so as to reduce the phase difference between the clock signal CLK and a dummy pattern signal DUMMY. The data signal Data is delayed in accordance with; the delay quantity which is set to the initializing period in an operation and transfer period. The phase difference reducing circuit 22 outputs the delayed data signal Data to an internal circuit 24 as the data signal Data'. The internal circuit 24 is operated in accordance with the clock signal CLK. For example, the internal circuit 24 responds to the edge of the clock signal CLK so as to fetch the data signal Data'.