Data cache fast address calculation system and method

摘要

The data cache features an improved mechanism for accessing data from the data memory array of a data cache, by generating a predicted address and using it to access the data cache array in parallel with the effective address computation. The logic circuitry consists of elements which are capable of performing a carry-free addition (logical or arithmetic) of a predetermined number of base register address bits with the same number of offset register address bits. Methods to generate and verify the predicted index are also provided.