| 摘要 |
<p>A trench process for establishing a contact for a semiconductor device with trenches such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs which reduces the number of masks and eliminates the need for lateral diffusion into the trench channel region. Control of the parasitic transistor in the trench MOSFET is also achieved. The cell size/pitch is reduced relative to conventional processes which require source block and P+ masks. <IMAGE></p> |
