发明名称 A/D CONVERTER
摘要 <p>PROBLEM TO BE SOLVED: To reduce the power consumption of an A/D conversion waiting period by providing a means for stopping bias circuits in the A/D conversion waiting period and supplying an A/D conversion operation timing signal to which the stable period of the restart time of the bias circuits is added at the time of A/D conversion to an A/D conversion part. SOLUTION: A stop signal generation circuit 12 always outputs an ON signal in an A/D conversion waiting state and stops the bias circuit 8 and the bias circuit 10. When an A/D conversion start trigger signal is inputted, a low power consumption conversion timing signal generation circuit 11 outputs the signal which is turned out in the period obtained by adding the period T2 until the respective circuits of the bias circuit 8 and the bias circuit 10 become stable at the time of restarting to the period T1 required for A/D conversion when an A/D conversion start trigger is inputted. Since a sample-and-hold circuit 2 executes an operation after the T2 period elapses after the bias circuit 8 and the bias circuit 10 are restarted and output voltage is stabilized and therefore A/D conversion can be executed without damaging conversion precision.</p>
申请公布号 JPH114167(A) 申请公布日期 1999.01.06
申请号 JP19970172820 申请日期 1997.06.13
申请人 NEC CORP 发明人 NAGAHAMA KENICHI
分类号 G06F1/32;H03M1/12;H03M1/38;(IPC1-7):H03M1/38 主分类号 G06F1/32
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