发明名称 |
Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages |
摘要 |
In a dynamic RAM of a CSL system, a memory array is divided into a plurality of memory array portions, and bit line pairs provided in the respective memory array portions are connected to their corresponding I/O line pairs simultaneously in response to a CSL output. In such an RAM, only the I/O line pair of a memory array portion to be accessed is precharged to the level of VCC-Vth, while the I/O line pair of a memory array portion not to be accessed is precharged to the level of +E,fra 1/2+EE xVCC which is the same level as the bit line pairs. This makes it possible to achieve a faster data reading operation and also prevent unnecessary currents from flowing between the bit line pairs and the I/O line pair in the unaccessed memory array portion.
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申请公布号 |
USRE36027(E) |
申请公布日期 |
1999.01.05 |
申请号 |
US19960664081 |
申请日期 |
1996.06.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIMOTO, KAZUTAMI;FUJISHIMA, KAZUYASU;HIDAKA, HIDETO;TSUKUDE, MASAKI;OHISHI, TSUKASA |
分类号 |
G11C11/409;G11C7/10;G11C7/12;G11C11/401;G11C11/4094;G11C11/4096;G11C11/41;H01L27/10;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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