| 摘要 |
PCT No. PCT/JP95/01767 Sec. 371 Date Jan. 20, 1998 Sec. 102(e) Date Jan. 20, 1998 PCT Filed Sep. 6, 1995A test pattern generation apparatus and method for an SDRAM can easily generate a test pattern for the SDRAM by having a specific wrap conversion circuit or an address conversion method. The wrap conversion circuit is provided to receive two kinds of data from a pattern generator and converts the data through a predetermined logic circuit information. The test pattern generation method for the SDRAM is carried out by inputting the column address data Y0-Y2 and the wrap address data Z0-Z2, and by generating output data which has been converted by a predetermined logic equation. The test pattern generation apparatus and method can also include an address inversion scramble for the converted output.
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