| 摘要 |
A method for forming multilevel interconnects in a semiconductor IC device is provided. The method involves a simplified planarization process for planarization of inter-metal dielectrics that allows for easy and cost-effective fabrication of the device. By this method, an insulating layer is formed over a substrate, then a first conductive layer is formed over the insulating layer and which is selectively removed to form conductive interconnects. Subsequently, a dielectric layer is formed over the conductive interconnects. A photoresist layer is then formed and patterned over the dielectric layer by a spin-coating process. An etching process is then conducted on the photoresist layer and the dielectric layer with a 1:1 etching ratio until the photoresist layer is completely removed. At the same moment when the photoresist layer is completely removed, the via holes are formed. The following steps are the same for fabricating the next-level interconnects. In the foregoing method, the spin-coating process allows the photoresist layer to be formed with a flat top surface. In the etching process, the 1:1 etching ratio on the photoresist layer and the dielectric layer allows the underlying dielectric layer to have a flat top surface when the photoresist layer is completely removed. The planarization process is significantly simplified. This allows the manufacturing costs to be significantly reduced.
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