| 摘要 |
<p>PROBLEM TO BE SOLVED: To make an delay amount to be corrected a minimum delay time unit of each delay circuit row by making plural hold circuits connect inputs to each output terminal of a 1st delay circuit row, connecting the output to a terminal which selects an input terminal in 2nd to N-th delay circuit rows, serially connecting the 2nd to the N-th delay circuit rows for the propagation of a clock signal and also making the order of connecting regular. SOLUTION: When an external clock 120 is inputted to a 1st delay circuit 101, one of continuous pulses first goes into a clock buffer 111 in a 1st delay circuit row 101 and decides a pulse width tPW. The width tPW is designed to be longer than the delay time length t110 of the row 101 in a basic circuit unit 110. A pulse that becomes the width of tPW proceeds through the row 101, and an output terminal which is connected to a hold circuit row 109 also performs L-H-L changes, accompanying the progress of the pulse.</p> |
