| 摘要 |
PROBLEM TO BE SOLVED: To provide an accurate evaluation method for parasitic source resistance in which there is no procedure for calculating values by plotting which may cause errors but required in the conventional technology. SOLUTION: After an FET is brought into a linear area, while a drain current is varied from Id1, Id2=βId1, and Id3=βId2 (βis a constant) under a constant gate current, the corresponding bias voltages in normal direction Vg1, Vg2, and Vg3 are measured, and a parasitic source resistance Rs is calculated by an expression in which only the drain current values Id1, Id2, and Id3 and bias voltage values Vg1, Vg2, and Vg3 in the normal direction are included.
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