| 摘要 |
<p>PROBLEM TO BE SOLVED: To avoid generation of voltage not matching to the threshold value by inhibiting transfer to a signal line of the voltage level of one node of a latch circuit forming the connecting point of any one of a plurality of latch circuits when the node of the other latch circuit forming a connecting point of any one of the other latch circuits and the control circuit is in the low level. SOLUTION: When the threshold voltage of memory cell exceeds 0.4 V, the memory cell turns off by means of the write voltage to maintain the precharge voltage of bit line. The precharge voltage is received by M1 and high level of Q2 is input to M2. Therefore, when high level of read signal L1 is applied to M3, Q1B is grounded through M1, M2, M3 and Q1 is inverted. Since low level of Q2 of 00, 01 data is given to the gate of M6, M6 turns OFF to perfectly inhibit the write operation and thereby demerit of excessive writing operation to be occurring for the 00 data can be prevented.</p> |
